Many advances in computer technologies yield new Input/Output (I/O) channel interfaces with higher signaling speeds and more functions. As new I/O channel interfaces are introduced, they can obviously be used to interconnect identical new systems, but it is very desirable to connect some number of the previous system generation computers into the cluster. One solution is to provide a set of older I/O channel interfaces. Another solution is to provide new I/O channel interfaces that are capable of running in both the old and the new modes. However, this second approach may add considerable complexity in the line drivers and receivers of the channel interface. For example, clock extraction at multiple signaling speeds requires special circuits. An even more difficult problem is the operating voltages. The operating voltages of silicon circuitry continue to decrease as device geometries shrink. As a consequence, the I/O channel signaling voltages are also getting smaller. In fact, the newer I/O channel receiver circuits cannot tolerate the voltage swings of the older I/O channel driver circuits. This sometimes makes it impractical to have I/O channel driver and receiver circuits that can operate in multiple modes.
It is also known to add a converter that connects the new I/O channel interface to the old I/O channel interface. Such a converter includes at least one old I/O channel interface operating at its speed and voltage and at least one new I/O channel interface operating at its speed and voltage. Data buffering in the converter is required to handle the speed differences between the old and new I/O channel interfaces. Since the old I/O channel interface usually operates at a slower speed than the new I/O channel interface, it is desirable to have a converter that connects one of the new I/O channel interfaces to more than one of the old I/O channel interfaces. Depending on the complexity of the I/O channel interface protocol, the converter can quickly become far too complicated to be practical.